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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
Rev. 05 -- 15 June 2009 Product data sheet
1. General description
The PCA9674/74A provide general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus (Fm+) family. The PCA9674/74A is a drop-in upgrade for the PCF8574/74A providing higher Fast-mode Plus I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without the need for bus buffers, higher total package sink capacity (200 mA versus 100 mA) that supports having all LEDs on at the same time and more device addresses (64 versus 8) are available to allow many more devices on the bus without address conflicts. The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCA9674/74A have low current consumption and include latched outputs with 25 mA high current drive capability for directly driving LEDs. They also possess an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. The internal Power-On Reset (POR) or Software Reset sequence initializes the I/Os as inputs.
2. Features
I I I I I I I I I I I I I 1 MHz I2C-bus interface Compliant with the I2C-bus Fast and Standard modes SDA with 30 mA sink capability for 4000 pF buses 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 8-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 200 mA Active LOW open-drain interrupt output 64 programmable slave addresses using 3 address pins Readable device ID (manufacturer, device type, and revision) Low standby current -40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA I Packages offered: SO16, SSOP20, TSSOP16, HVQFN16
3. Applications
I I I I I I I I LED signs and displays Servers Industrial control Medical equipment PLCs Cellular telephones Gaming machines Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information Topside mark 674 74A PCA9674D PCA9674AD PCA9674 PA9674A PCA9674 PA9674A SSOP20 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic shrink small outline package; 20 leads; body width 4.4 mm SOT403-1 SOT266-1 SO16 Package Name HVQFN16 Description Version plastic thermal enhanced very thin quad flat package; no leads; SOT758-1 16 terminals; body 3 x 3 x 0.85 mm plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 Type number PCA9674BS PCA9674ABS PCA9674D PCA9674AD PCA9674PW PCA9674APW PCA9674TS PCA9674ATS
PCA9674_PCA9674A_5
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Product data sheet
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
5. Block diagram
PCA9674 PCA9674A
INT AD0 AD1 AD2 SCL SDA INPUT FILTER
INTERRUPT LOGIC
LP FILTER
I2C-BUS CONTROL
SHIFT REGISTER
8 BITS
I/O PORT
P0 to P7
write pulse read pulse VDD VSS POWER-ON RESET
002aac108
Fig 1.
Block diagram of PCA9674/74A
write pulse Itrt(pu) data from Shift Register D FF CI S power-on reset D FF read pulse CI S Q Q
100 A
IOH
VDD
IOL
P0 to P7
VSS
data to Shift Register
002aac109
to interrupt logic
Fig 2.
Simplified schematic diagram of P0 to P7
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Product data sheet
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
6. Pinning information
6.1 Pinning
AD0 AD1 AD2 P0 P1 P2 P3 VSS
1 2 3 4 5 6 7 8
002aac111
16 VDD 15 SDA 14 SCL 13 INT 12 P7 11 P6 10 P5 9 P4
AD0 AD1 AD2 P0 P1 P2 P3 VSS
1 2 3 4 5 6 7 8
002aac113
16 VDD 15 SDA 14 SCL 13 INT 12 P7 11 P6 10 P5 9 P4
PCA9674D PCA9674AD
PCA9674PW PCA9674APW
Fig 3.
Pin configuration for SO16
Fig 4.
Pin configuration for TSSOP16
PCA9674BS PCA9674ABS
INT SCL n.c. SDA VDD AD0 AD1 n.c. AD2
1 2 3 4 5 6 7 8 9
20 P7 19 P6 18 n.c. 17 P5 16 P4 15 VSS 14 P3 13 n.c. 12 P2 11 P1
002aac112
terminal 1 index area
AD2 P0 P1 P2
1 2 3 4 5 6 7 8
13 SDA 12 SCL 11 INT 10 P7 9 P6 P5
16 AD1
15 AD0 VSS
PCA9674TS PCA9674ATS
P3
P0 10
P4
14 VDD
002aac114
Transparent top view
Fig 5.
Pin configuration for SSOP20
Fig 6.
Pin configuration for HVQFN16
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Product data sheet
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
6.2 Pin description
Table 2. Symbol AD0 AD1 AD2 P0 P1 P2 P3 VSS P4 P5 P6 P7 INT SCL SDA VDD Table 3. Symbol INT SCL n.c. SDA VDD AD0 AD1 n.c. AD2 P0 P1 P2 n.c. P3 VSS P4 P5 n.c. P6 P7 Pin description for SO16, TSSOP16 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description address input 0 address input 1 address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 quasi-bidirectional I/O 6 quasi-bidirectional I/O 7 interrupt output (active LOW) serial clock line serial data line supply voltage
Pin description for SSOP20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description interrupt output (active LOW) serial clock line not connected serial data line supply voltage address input 0 address input 1 not connected address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 not connected quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 not connected quasi-bidirectional I/O 6 quasi-bidirectional I/O 7
PCA9674_PCA9674A_5
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Product data sheet
Rev. 05 -- 15 June 2009
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
Pin description for HVQFN16 Pin 1 2 3 4 5 Description address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 quasi-bidirectional I/O 6 quasi-bidirectional I/O 7 interrupt output (active LOW) serial clock line serial data line supply voltage address input 0 address input 1
Table 4. Symbol AD2 P0 P1 P2 P3 VSS P4 P5 P6 P7 INT SCL SDA VDD AD0 AD1
[1]
[1]
6 7 8 9 10 11 12 13 14 15 16
HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to Figure 1 "Block diagram of PCA9674/74A".
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9674/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of 64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 5 "PCA9674 address map" and Table 6 "PCA9674A address map". Remark: When using the PCA9674A, the General Call address (0000 0000b) and the Device ID address (1111 100Xb) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA9674A not to acknowledge. Remark: When using the PCA9674 or the PCA9674A, reserved I2C-bus addresses must be used with caution since they can interfere with:
* "reserved for future use" I2C-bus addresses (0000 011, 1111 101, 1111 110,
1111 111)
* slave devices that use the 10-bit addressing scheme (1111 0xx) * High speed mode (Hs-mode) master code (0000 1xx)
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Product data sheet
Rev. 05 -- 15 June 2009
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
slave address A6 A5 A4 A3 A2 A1 A0 R/W
programmable
002aab636
Fig 7.
PCA9674/74A address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 or PCF8574A is applied.
7.1.1 Address maps
Table 5. AD2 VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD PCA9674 address map AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh
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Product data sheet
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
PCA9674 address map ...continued AD1 VSS VSS VDD VDD VSS VSS VDD VDD SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD AD0 SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh A0h A2h A4h A6h A8h AAh ACh AEh B0h B2h B4h B6h B8h BAh BCh BEh C0h C2h C4h C6h C8h CAh CCh CEh E0h E2h E4h E6h E8h EAh ECh EEh
Table 5. AD2 VSS VSS VSS VSS VDD VDD VDD VDD SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA
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Product data sheet
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
PCA9674A address map AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD SCL SCL SDA SDA SCL SCL SDA SDA AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh
Table 6. AD2 VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD SCL SCL SCL SCL SDA SDA SDA SDA
PCA9674_PCA9674A_5
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Product data sheet
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
PCA9674A address map ...continued AD1 SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD AD0 SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address D0h D2h D4h D6h D8h DAh DCh DEh F0h F2h F4h F6h -[1] FAh FCh FEh -[1] 02h 04h 06h 08h 0Ah 0Ch 0Eh
Table 6. AD2 SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA
[1]
The PCA9674A does not acknowledge when AD2, AD1, AD0 follows this configuration.
7.2 Software Reset Call, and device ID addresses
Two other different addresses can be sent to the PCA9674/74A.
* General Call address: allows to reset the PCA9674/74A through the I2C-bus upon
reception of the right I2C-bus sequence. See Section 7.2.1 "Software Reset" for more information.
* Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 7.2.2 "Device ID (PCA9674/74A ID field)" for more information.
R/W 0 0 0 0 0 0 0 0
002aac115
Fig 8.
General Call address
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
1
1
1
1
1
0
0
R/W
002aac116
Fig 9.
Device ID address
7.2.1 Software Reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call I2C-bus address `0000 000' with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9674/74A device(s) acknowledge(s) after seeing the General Call address `0000 0000' (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h. a. The PCA9674/74A acknowledges this value only. If the byte is not equal to 06h, the PCA9674/74A does not acknowledge it. If more than 1 byte of data is sent, the PCA9674/74A does not acknowledge any more. 5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9674/74A then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. The I2C-bus master must interpret a non-acknowledge from the PCA9674/74A (at any time) as a `Software Reset Abort'. The PCA9674/74A does not initiate a reset of its registers. The unique sequence that initiates a Software Reset is described in Figure 10.
SWRST Call I2C-bus address S 0 0 0 0 0 0 0 0 R/W acknowledge from slave(s) A 0
SWRST data = 06h 0 0 0 0 1 1 0 A P
START condition
acknowledge from slave(s)
PCA9674/74A is(are) reset. Registers are set to default power-up values.
002aac262
Fig 10. Software Reset sequence
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
7.2.2 Device ID (PCA9674/74A ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:
* 8 bits with the manufacturer name, unique per manufacturer (for example, NXP). * 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the
category ID and the 6 LSBs with the feature ID (for example, for example PCA9674/74A 16-bit quasi-output I/O expander).
* 3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows: 1. START command 2. The master sends the Reserved Device ID I2C-bus address `1111 100' with the R/W bit set to 0 (write). 3. The master sends the I2C-bus slave address of the slave device it needs to identify. The LSB is a `Don't care' value. Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 4. The master sends a Re-START command. Remark: A STOP command followed by a START command will reset the slave state machine and the Device ID read cannot be performed. Remark: A STOP command or a Re-START command followed by an access to another slave device will reset the slave state machine and the Device ID read cannot be performed. 5. The master sends the Reserved Device ID I2C-bus address `1111 100' with the R/W bit set to 1 (read). 6. The device ID read can be done, starting with the 8 manufacturer bits (first byte + 4 MSB of the second byte), followed by the 13 part identification bits and then the 3 die revision bits (3 LSB of the third byte). 7. The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. Remark: The reading of the Device ID can be stopped anytime by sending a NACK command. Remark: If the master continues to ACK the bytes after the third byte, the PCA9674/74A rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. For the PCA9674/74A, the Device ID is as shown in Figure 11.
manufacturer
0
0
0
0
0
0
0
0
part identification
0
0
0
0
0
0
1
0
0
1
0
1
1
category identification
feature identification revision 0 0 0
002aac118
Fig 11. PCA9674/74A ID
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Product data sheet
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
acknowledge from one or several slave(s) device ID address S 1 1 1 1 1 0 0 0 R/W don't care A A6 A5 A4 A3 A2 A1 A0 X I2C-bus slave address of the device to be identified acknowledge from master
acknowledge from slave to be identified acknowledge from slave to be identified A 1 1 1 1 1 0 0 1 R/W A
START condition
device ID address acknowledge from master
no acknowledge from master P
M7 M6 M5 M4 M3 M2 M1 M0 A C6 C5 C4 C3 C2 C1 C0 F5 A F4 P3 P2 P1 P0 R2 R1 R0 A category identification = 0000001 revision = 000 feature identification = 001011
manufacturer name = 00000000
STOP condition
002aac119
If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a `no acknowledge'.
Fig 12. Device ID field reading
8. I/O programming
8.1 Quasi-bidirectional I/O architecture
The PCA9674/74A's 8 ports (see Figure 2) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see Figure 14). Output data is transmitted to the ports in the Write mode (see Figure 13). This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS.
8.2 Writing to the port (Output mode)
To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the write mode is entered. The PCA9674/74A acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the PCA9674/74A. The 8-bit data is presented on the port lines after it has been acknowledged by the PCA9674/74A. The number of data bytes that can be sent successively is not limited. The previous data is overwritten every time a data byte has been sent.
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Product data sheet
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NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
SCL
1
2
3
4
5
6
7
8
9 data 1 data 2
slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 START condition R/W
A P7 P6 1 P4 P3 P2 P1 P0 A P7 P6 0 P4 P3 P2 P1 P0 A P5 acknowledge from slave P5 acknowledge from slave tv(Q) acknowledge from slave
write to port tv(Q) DATA 1 VALID DATA 2 VALID
data output from port P5 output voltage
P5 pull-up output current INT
Itrt(pu) IOH
td(rst)
002aae524
Fig 13. Write mode (output)
8.3 Reading from a port (Input mode)
All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered. The data bytes that follow on the SDA are the values on the ports. If the data on the input port changes faster than the master can read, this data may be lost.
slave address SDA S A6 A5 A4 A3 A2 A1 A0 1 START condition read from port R/W A
data from port DATA 1 A
data from port DATA 4
no acknowledge from master
1
P STOP condition
acknowledge from slave
acknowledge from master
DATA 2 data into port th(D) INT tv(D) td(rst) td(rst)
002aae525
DATA 3 tsu(D)
DATA 4
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input data is lost.
Fig 14. Read input port register
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9674/74A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9674/74A registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset the device.
8.5 Interrupt output (INT)
The PCA9674/74A provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see Figure 13, Figure 14, and Figure 15). This gives these chips a kind of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the signal INT is valid. The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely deactivated (HIGH). The interrupt is reset in the read mode on the rising edge of the read from port pulse. During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as an INT.
VDD
device 1
device 2
device 8
PCA9674
MICROCOMPUTER INT INT
PCA9674
PCA9674
INT
INT
002aac122
Fig 15. Application of multiple PCA9674s with interrupt
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 16).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 16. Bit transfer
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 17).
SDA
SCL S START condition P STOP condition
mba608
Fig 17. Definition of START and STOP conditions
9.2 System configuration
A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 18).
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER
SLAVE
002aaa966
Fig 18. System configuration
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 19. Acknowledgement on the I2C-bus
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 20, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I2C-bus.
VDD
VDD VDD
CORE PROCESSOR
SDA SCL INT
AD0 AD1 AD2
P0 P1 P2 P3 P4 P5 P6 P7
temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3
002aac123
Fig 20. Bidirectional I/O expander application
10.2 High current-drive load applications
The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200 mA.
VDD
VDD
VDD
CORE PROCESSOR
SDA SCL INT
AD0 AD1 AD2
P0 P1 P2 P3 P4 P5 P6 P7
LOAD
002aac124
Fig 21. High current-drive load application
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
11. Limiting values
Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD ISS VI II IO Ptot P/out Tstg Tamb
[1]
Parameter supply voltage supply current ground supply current input voltage input current output current total power dissipation power dissipation per output storage temperature ambient temperature
Conditions
Min -0.5 VSS - 0.5 [1]
Max +6 100 400 5.5 20 50 400 100 +150 +85
Unit V mA mA V mA mA mW mW C C
-65
operating
-40
Total package (maximum) output current is 400 mA.
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
12. Static characteristics
Table 8. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD IDD supply voltage supply current Operating mode; no load; VI = VDD or VSS; fSCL = 1 MHz; AD0, AD1, AD2 = static H or L Standby mode; no load; VI = VDD or VSS; fSCL = 0 kHz
[1]
Parameter
Conditions
Min 2.3 -
Typ 200
Max 5.5 500
Unit V A
Istb VPOR VIL VIH IOL
standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current
-0.5 0.7VDD
4.5 1.8 35 44 57 5 26 33 40 -138 -1.0 2.1 2.1 3 3.5
10 2.0 +0.3VDD 5.5 +1 10 200 -300 10 10 5 +0.3VDD 5.5 +1 5
A V V V mA mA mA A pF mA mA mA mA A mA pF pF mA pF V V A pF
Input SCL; input/output SDA
VOL = 0.4 V; VDD = 2.3 V VOL = 0.4 V; VDD = 3.0 V VOL = 0.4 V; VDD = 4.5 V
20 25 30 -1 [2] [2] [2] [2]
IL Ci IOL
leakage current input capacitance LOW-level output current
VI = VDD or VSS VI = VSS VOL = 0.5 V; VDD = 2.3 V VOL = 0.5 V; VDD = 3.0 V VOL = 0.5 V; VDD = 4.5 V
I/Os; P0 to P7 12 17 25 -30 -0.5
[3] [3]
IOL(tot) IOH Itrt(pu) Ci Co IOL Co VIL VIH ILI Ci
[1] [2] [3]
total LOW-level output current HIGH-level output current input capacitance output capacitance LOW-level output current output capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance
VOL = 0.5 V; VDD = 4.5 V VOH = VSS
transient boosted pull-up current VOH = VSS; see Figure 13
3.0 -0.5 0.7VDD -1 -
Interrupt INT (see Figure 14 and Figure 13) VOL = 0.4 V
Inputs AD0, AD1, AD2
VDD must be lowered to 0.2 V or less in order to reset part. Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits. The value is verified by characterization.
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
13. Dynamic characteristics
Table 9. Dynamic characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Standard mode Fast mode I2C-bus Fast-mode Plus Unit I2C-bus I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time[1] data valid time[2] data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter[6] data output valid time data input set-up time data input hold time data input valid time reset delay time
[4][5]
Max 100 3.45 300 1000 50
Min 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] -
Max 400 0.9 300 300 50
Min 0 0.5 0.26 0.26 0.26 0 0.05 50 50 0.5 0.26 -
Max 1000 0.45 450 120 120 50 kHz s s s s ns s ns ns s s ns ns ns
0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 -
Port timing; CL 100 pF (see Figure 13 and Figure 14) tv(Q) tsu(D) th(D) tv(D) td(rst)
[1] [2] [3] [4] [5]
0 4 -
4 4 4
0 4 -
4 4 4
0 4 -
4 4 4
s s s s s
Interrupt timing; CL 100 pF (see Figure 13 and Figure 14)
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL's falling edge. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
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[6]
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Rise and fall times refer to VIL and VIH.
Fig 22. I2C-bus timing diagram
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
14. Package outline
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm
SOT758-1
D
B
A
terminal 1 index area
E
A A1 c
detail X
e1
1/2 e
C vMCAB wM C 8 y1 C y
e 5 L 4
b
9 e
Eh
1/2 e
e2
1
12
terminal 1 index area
16 Dh 0
13 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.75 1.45 E (1) 3.1 2.9 Eh 1.75 1.45 e 0.5 e1 1.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT758-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21
Fig 23. Package outline SOT758-1 (HVQFN16)
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013 JEITA EUROPEAN PROJECTION A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8o o 0
ISSUE DATE 99-12-27 03-02-19
Fig 24. Package outline SOT162-1 (SO16)
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 25. Package outline SOT403-1 (TSSOP16)
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
D
E
A X
c y HE vM A
Z
20
11
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
10
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 o 0
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC MO-152 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 26. Package outline SOT266-1 (SSOP20)
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 11. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 27.
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Abbreviations
Table 12. Acronym CDM ESD GPIO HBM LED IC I2C-bus ID LSB MM MSB PLC PWM SMBus Abbreviations Description Charged Device Model ElectroStatic Discharge General Purpose Input/Output Human Body Model Light Emitting Diode Integrated Circuit Inter-Integrated Circuit bus Identification Least Significant Bit Machine Model Most Significant Bit Programmable Logic Controller Pulse Width Modulation System Management Bus
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
18. Revision history
Table 13. Revision history Release date 20090615 Data sheet status Product data sheet Change notice Supersedes PCA9674_PCA9674A_4 Document ID PCA9674_PCA9674A_5 Modifications:
*
Table 8 "Static characteristics": - Table note [1] re-written. - Table note [3] re-written.
PCA9674_PCA9674A_4 PCA9674_PCA9674A_3 PCA9674_PCA9674A_2 PCA9674_PCA9674A_1
20090303 20070907 20061012 20060905
Product data sheet Product data sheet Product data sheet Objective data sheet
-
PCA9674_PCA9674A_3 PCA9674_PCA9674A_2 PCA9674_PCA9674A_1 -
PCA9674_PCA9674A_5
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Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9674_PCA9674A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 June 2009
31 of 32
NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
21. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.2.1 7.2.2 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.1.1 9.2 9.3 10 10.1 10.2 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software Reset Call, and device ID addresses 10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 11 Device ID (PCA9674/74A ID field) . . . . . . . . . 12 I/O programming . . . . . . . . . . . . . . . . . . . . . . . 13 Quasi-bidirectional I/O architecture . . . . . . . . 13 Writing to the port (Output mode) . . . . . . . . . . 13 Reading from a port (Input mode) . . . . . . . . . 14 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 15 Characteristics of the I2C-bus. . . . . . . . . . . . . 16 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 START and STOP conditions . . . . . . . . . . . . . 16 System configuration . . . . . . . . . . . . . . . . . . . 16 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application design-in information . . . . . . . . . 18 Bidirectional I/O expander applications . . . . . 18 High current-drive load applications . . . . . . . . 18 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 Static characteristics. . . . . . . . . . . . . . . . . . . . 20 Dynamic characteristics . . . . . . . . . . . . . . . . . 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Handling information. . . . . . . . . . . . . . . . . . . . 27 Soldering of SMD packages . . . . . . . . . . . . . . 27 Introduction to soldering . . . . . . . . . . . . . . . . . 27 Wave and reflow soldering . . . . . . . . . . . . . . . 27 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 19.4 20 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information . . . . . . . . . . . . . . . . . . . . 31 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 June 2009 Document identifier: PCA9674_PCA9674A_5

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